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ICCAD
2009
IEEE
96views Hardware» more  ICCAD 2009»
14 years 9 months ago
PSTA-based branch and bound approach to the silicon speedpath isolation problem
The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The ide...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
CAV
2004
Springer
101views Hardware» more  CAV 2004»
15 years 5 months ago
Symbolic Model Checking of Non-regular Properties
This paper presents a symbolic model checking algorithm for Fixpoint Logic with Chop, an extension of the modal µ-calculus capable of defining non-regular properties. Some empiri...
Martin Lange
ATVA
2004
Springer
115views Hardware» more  ATVA 2004»
15 years 3 months ago
First-Order LTL Model Checking Using MDGs
In this paper, we describe a first-order linear time temporal logic (LTL) model checker based on multiway decision graphs (MDG). We developed a first-order temporal language, LMDG ...
Fang Wang, Sofiène Tahar, Otmane Aït M...
RE
2001
Springer
15 years 4 months ago
Events and Constraints: A Graphical Editor for Capturing Logic Requirements of Programs
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
Margaret H. Smith, Gerard J. Holzmann, Kousha Etes...
FM
2003
Springer
174views Formal Methods» more  FM 2003»
15 years 5 months ago
Model-Checking TRIO Specifications in SPIN
We present a novel application on model checking through SPIN as a means for verifying purely descriptive specifications written in TRIO, a first order, linear-time temporal logic ...
Angelo Morzenti, Matteo Pradella, Pierluigi San Pi...