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» Model Checking CTL Properties of Pushdown Systems
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ASWEC
2007
IEEE
15 years 7 months ago
Timed Behavior Trees and Their Application to Verifying Real-Time Systems
Behavior Trees (BTs) are a graphical notation used for formalising functional requirements and have been successfully applied to several case studies. However, the notation curren...
Lars Grunske, Kirsten Winter, Robert Colvin
ICCD
1995
IEEE
109views Hardware» more  ICCD 1995»
15 years 5 months ago
Verifying the performance of the PCI local bus using symbolic techniques
Symbolic model checking is a successful technique for checking properties of large finite-state systems. This method has been used to verify a number of real-world hardware desig...
Sérgio Vale Aguiar Campos, Edmund M. Clarke...
FORMATS
2005
Springer
15 years 7 months ago
Diagonal Constraints in Timed Automata: Forward Analysis of Timed Systems
Timed automata (TA) are a widely used model for real-time systems. Several tools are dedicated to this model, and they mostly implement a forward analysis for checking reachability...
Patricia Bouyer, François Laroussinie, Pier...
CONCUR
2008
Springer
15 years 3 months ago
Spatial and Behavioral Types in the Pi-Calculus
We present a framework that combines ideas from spatial logics and Igarashi and Kobayashi's behavioural type systems, drawing benefits from both. In our approach, type systems...
Lucia Acciai, Michele Boreale
ISMVL
2010
IEEE
188views Hardware» more  ISMVL 2010»
15 years 6 months ago
MDGs Reduction Technique Based on the HOL Theorem Prover
—Multiway Decision Graphs (MDGs) subsume Binary Decision Diagrams (BDDs) and extend them by a first-order formulae suitable for model checking of data path circuits. In this pap...
Sa'ed Abed, Otmane Aït Mohamed