189 search results - page 8 / 38 » Model Checking Correctness Properties of Electronic Contract... |
115
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DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
FUIN
2007
14 years 11 months ago
2007
In this paper we offer a novel methodology for verifying correctness of (timed) security protocols. The idea consists in computing the time of a correct execution of a session and ...
1701
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ICECCS
2008
IEEE
15 years 6 months ago
2008
IEEE
Component-based software development focuses on building large software systems by integrating existing software components to reduce cost, risk and time. However, behavioural and...
ATVA
2006
Springer
15 years 3 months ago
2006
Springer
Of special interest in formal verification are safety properties, which assert that the system always stays within some allowed region. Each safety property can be associated with...
114
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FMCAD
2008
Springer
15 years 1 months ago
2008
Springer
el Sequential Memory Abstraction for Model Checking Per Bjesse Advanced Technology Group Synopsys Inc. Many designs intermingle large memories with wide data paths and nontrivial c...