2878 search results - page 220 / 576 » Model Checking FTA |
114
Voted
ISAAC
2007
Springer
15 years 9 months ago
2007
Springer
Checking value-sensitive data structures in sublinear space has been an open problem for over a decade. In this paper, we suggest a novel approach to solving it. We show that, in c...
117
Voted
PDPTA
2003
15 years 5 months ago
2003
We present a novel approach to parallel Boolean satisfiability (SAT) checking. A distinctive feature of our parallel SAT checker is that it incorporates all essential heuristics ...
140
Voted
TPHOL
2008
IEEE
15 years 10 months ago
2008
IEEE
Systems that can immediately react to their inputs may suffer from cyclic dependencies between their actions and the corresponding trigger conditions. For this reason, causality an...
142
Voted
CAV
2008
Springer
15 years 5 months ago
2008
Springer
Abstract. This paper develops a local reasoning method to check lineartime temporal properties of concurrent programs. In practice, it is often infeasible to model check over the p...
101
Voted
DATE
2010
IEEE
15 years 8 months ago
2010
IEEE
—Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Sp...