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» Model Checking Games for Branching Time Logics
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GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
15 years 5 months ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
CONCUR
2000
Springer
15 years 3 months ago
Model Checking with Finite Complete Prefixes Is PSPACE-Complete
Unfoldings are a technique for verification of concurrent and distributed systems introduced by McMillan. The method constructs a finite complete prefix, which can be seen as a sym...
Keijo Heljanko
CSL
2009
Springer
15 years 3 months ago
Tree-Width for First Order Formulae
We introduce tree-width for first order formulae , fotw(). We show that computing fotw is fixed-parameter tractable with parameter fotw. Moreover, we show that on classes of formul...
Isolde Adler, Mark Weyer
ICFEM
2009
Springer
14 years 9 months ago
Graded-CTL: Satisfiability and Symbolic Model Checking
In this paper we continue the study of a strict extension of the Computation Tree Logic, called graded-CTL, recently introduced by the same authors. This new logic augments the sta...
Alessandro Ferrante, Margherita Napoli, Mimmo Pare...
ENTCS
2007
158views more  ENTCS 2007»
14 years 11 months ago
Abstraction and Completeness for Real-Time Maude
ion and Completeness for Real-Time Maude Peter Csaba ¨Olveczky a,b and Jos´e Meseguer b a Department of Informatics, University of Oslo b Department of Computer Science, Universi...
Peter Csaba Ölveczky, José Meseguer