1463 search results - page 147 / 293 » Model Checking Implicit-Invocation Systems |
127
click to vote
VMCAI
2009
Springer
15 years 8 months ago
2009
Springer
Abstract. Symmetry reduction is a technique to alleviate state explosion in model checking by replacing a model of replicated processes with a bisimilar quotient model. The size of...
101
click to vote
CASSIS
2004
Springer
15 years 7 months ago
2004
Springer
The ESC/Java tool was a lauded advance in effective static checking of realistic Java programs, but has become out-of-date with respect to Java and the Java Modeling Language (JML...
132
click to vote
DATE
2009
IEEE
15 years 8 months ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
123
click to vote
VLSID
2003
IEEE
16 years 1 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
103
click to vote
CONCUR
1997
Springer
15 years 5 months ago
1997
Springer
Abstract. In a trace-based world, the modular speci cation, veri cation, and control of live systems require each module to be receptive that is, each module must be able to meet i...