1463 search results - page 55 / 293 » Model Checking Implicit-Invocation Systems |
120
Voted
ASPDAC
2007
ACM
15 years 5 months ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
101
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QEST
2008
IEEE
15 years 8 months ago
2008
IEEE
CaVi provides a uniform interface to state-of-the-art simulation methods and formal verification methods for wireless sensor network. Simulation is suitable to examine the behavi...
114
Voted
ACSD
2008
IEEE
15 years 3 months ago
2008
IEEE
The design of complex concurrent systems often involves intricate performance and dependability considerations. Continuous-time Markov chains (CTMCs) are widely used models for co...
109
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MEMOCODE
2007
IEEE
15 years 8 months ago
2007
IEEE
The always increasing complexity of digital system is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at difbstraction le...
128
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TACAS
2004
Springer
15 years 7 months ago
2004
Springer
Temporal logic is two-valued: formulas are interpreted as either true or false. When applied to the analysis of stochastic systems, or systems with imprecise formal models, tempor...