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» Model Checking Is Static Analysis of Modal Logic
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142
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POPL
2012
ACM
13 years 11 months ago
Playing in the grey area of proofs
Interpolation is an important technique in verification and static analysis of programs. In particular, interpolants extracted from proofs of various properties are used in invar...
Krystof Hoder, Laura Kovács, Andrei Voronko...
133
Voted
ICSE
2007
IEEE-ACM
16 years 3 months ago
Sequential Circuits for Relational Analysis
The Alloy tool-set has been gaining popularity as an alternative to traditional manual testing and checking for design correctness. Alloy uses a first-order relational logic for m...
Fadi A. Zaraket, Adnan Aziz, Sarfraz Khurshid
126
Voted
AMAST
2004
Springer
15 years 9 months ago
Formal JVM Code Analysis in JavaFAN
JavaFAN uses a Maude rewriting logic specification of the JVM semantics as the basis of a software analysis tool with competitive performance. It supports formal analysis of concu...
Azadeh Farzan, José Meseguer, Grigore Rosu
SAS
2007
Springer
112views Formal Methods» more  SAS 2007»
15 years 9 months ago
Taming the Wrapping of Integer Arithmetic
Variables in programs are usually confined to a fixed number of bits and results that require more bits are truncated. Due to the use of 32-bit and 64-bit variables, inadvertent ...
Axel Simon, Andy King
147
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DFG
2004
Springer
15 years 7 months ago
Verification of PLC Programs Given as Sequential Function Charts
Programmable Logic Controllers (PLC) are widespread in the manufacturing and processing industries to realize sequential procedures and to avoid safety-critical states. For the spe...
Nanette Bauer, Sebastian Engell, Ralf Huuck, Sven ...