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» Model Checking Large Network Protocol Implementations
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DATE
2005
IEEE
107views Hardware» more  DATE 2005»
15 years 7 months ago
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique
Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP ...
César A. M. Marcon, Ney Laert Vilar Calazan...
HICSS
2003
IEEE
146views Biometrics» more  HICSS 2003»
15 years 7 months ago
A Model for the Emergence and Diffusion of Software Standards
The economic impact of the growth dynamic of standards is often described from a macroeconomic point of view, employing network effect theory and models dealing with externalities...
Tim Stockheim, Michael Schwind, Wolfgang Köni...
MICRO
2009
IEEE
168views Hardware» more  MICRO 2009»
15 years 8 months ago
Ordering decoupled metadata accesses in multiprocessors
Hardware support for dynamic analysis can minimize the performance overhead of useful applications such as security checks, debugging, and profiling. To eliminate implementation ...
Hari Kannan
CAL
2010
14 years 10 months ago
SMT-Directory: Efficient Load-Load Ordering for SMT
Memory models like SC, TSO, and PC enforce load-load ordering, requiring that loads from any single thread appear to occur in program order to all other threads. Out-of-order execu...
A. Hilton, A. Roth
ISPASS
2010
IEEE
15 years 7 months ago
A study of hardware assisted IP over InfiniBand and its impact on enterprise data center performance
— High-performance sockets implementations such as the Sockets Direct Protocol (SDP) have traditionally showed major performance advantages compared to the TCP/IP stack over Infi...
Ryan E. Grant, Pavan Balaji, Ahmad Afsahi