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» Model Checking Large Network Protocol Implementations
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VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 4 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
143
Voted
NAACL
1994
15 years 5 months ago
A One Pass Decoder Design For Large Vocabulary Recognition
To achieve reasonable accuracy in large vocabulary speech recognition systems, it is important to use detailed acoustic models together with good long span language models. For ex...
J. J. Odell, V. Valtchev, Philip C. Woodland, S. J...
IPPS
2010
IEEE
15 years 1 months ago
Runtime checking of serializability in software transactional memory
Abstract--Ensuring the correctness of complex implementations of software transactional memory (STM) is a daunting task. Attempts have been made to formally verify STMs, but these ...
Arnab Sinha, Sharad Malik
MSWIM
2004
ACM
15 years 9 months ago
Consistency challenges of service discovery in mobile ad hoc networks
Emerging “urban” ad hoc networks resulting from a large number of individual WLAN users challenge the way users could explore and interact with their physical surroundings. Ro...
Christian Frank, Holger Karl
CN
2007
99views more  CN 2007»
15 years 4 months ago
Design and implementation of a secure wide-area object middleware
Wide-area service replication is becoming increasingly common, with the emergence of new operational models such as content delivery networks and computational grids. This paper d...
Bogdan C. Popescu, Bruno Crispo, Andrew S. Tanenba...