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VMCAI
2004
Springer
15 years 7 months ago
2004
Springer
DATE
2003
IEEE
15 years 7 months ago
2003
IEEE
: Binary Decision Diagrams (BDDs) have been widely used in synthesis and verification. Boolean Satisfiability (SAT) Solvers, on the other hand, have been gaining
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ISMVL
2003
IEEE
15 years 7 months ago
2003
IEEE
In earlier work [9], we defined CTL model-checking over finite-valued logics with De Morgan negation. In this paper, we extend this work to logics with intuitionistic, Galois an...
LICS
2003
IEEE
15 years 7 months ago
2003
IEEE
