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DAC
2003
ACM
16 years 2 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
FTCS
1998
114views more  FTCS 1998»
15 years 3 months ago
Verification of a Safety-Critical Railway Interlocking System with Real-Time Constraints
Ensuring the correctness of computer systems used in lifecritical applications is very difficult. The most commonly used verification methods, simulation and testing, are not exha...
Vicky Hartonas-Garmhausen, Sérgio Vale Agui...
ATAL
2009
Springer
15 years 8 months ago
Abstraction in model checking multi-agent systems
ion in model checking multi-agent systems Mika Cohen Department of Computing Imperial College London London, UK Mads Dam Access Linnaeus Center Royal Institute of Technology Stockh...
Mika Cohen, Mads Dam, Alessio Lomuscio, Francesco ...
GLVLSI
2009
IEEE
150views VLSI» more  GLVLSI 2009»
15 years 8 months ago
Contradictory antecedent debugging in bounded model checking
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
Daniel Große, Robert Wille, Ulrich Kühn...
115
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KBSE
2009
IEEE
15 years 8 months ago
SMT-Based Bounded Model Checking for Embedded ANSI-C Software
Propositional bounded model checking has been applied successfully to verify embedded software but is limited by the increasing propositional formula size and the loss of structur...
Lucas Cordeiro, Bernd Fischer, João Marques...