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ATVA
2008
Springer
131views Hardware» more  ATVA 2008»
15 years 5 months ago
Computation Tree Regular Logic for Genetic Regulatory Networks
Model checking has proven to be a useful analysis technique not only for concurrent systems, but also for the genetic regulatory networks (Grns) that govern the functioning of livi...
Radu Mateescu, Pedro T. Monteiro, Estelle Dumas, H...
144
Voted
ATAL
2006
Springer
15 years 7 months ago
On the complexity of practical ATL model checking
We investigate the computational complexity of reasoning about multi-agent systems using the cooperation logic ATL of Alur, Henzinger, and Kupferman. It is known that satisfiabili...
Wiebe van der Hoek, Alessio Lomuscio, Michael Wool...
JOLLI
2007
128views more  JOLLI 2007»
15 years 3 months ago
Linear temporal logic as an executable semantics for planning languages
This paper presents an approach to artificial intelligence planning based on linear temporal logic (LTL). A simple and easy-to-use planning language is described, PDDL-K (Planning...
Marta Cialdea Mayer, Carla Limongelli, Andrea Orla...
ACSD
2005
IEEE
162views Hardware» more  ACSD 2005»
15 years 9 months ago
Complexity Results for Checking Distributed Implementability
We consider the distributed implementability problem as: Given a labeled transition system TS together with a distribution ∆ of its actions over a set of processes, does there ex...
Keijo Heljanko, Alin Stefanescu
138
Voted
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
15 years 7 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...