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186
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ICCS
2007
Springer
15 years 7 months ago
Building Verifiable Sensing Applications Through Temporal Logic Specification
Abstract. Sensing is at the core of virtually every DDDAS application. Sensing applications typically involve distributed communication and coordination over large self-organized n...
Asad Awan, Ahmed H. Sameh, Suresh Jagannathan, Ana...
258
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EH
1999
IEEE
351views Hardware» more  EH 1999»
15 years 8 months ago
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints
Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraint...
Marek A. Perkowski, Alan Mishchenko, Anatoli N. Ch...
146
Voted
MEMOCODE
2003
IEEE
15 years 9 months ago
LOTOS Code Generation for Model Checking of STBus Based SoC: the STBus interconnect
In the design process of SoC (System on Chip), validation is one of the most critical and costly activity. The main problem for industrial companies like STMicroelectronics, stand...
Pierre Wodey, Geoffrey Camarroque, Fabrice Baray, ...
159
Voted
CONCUR
1997
Springer
15 years 7 months ago
Reachability Analysis of Pushdown Automata: Application to Model-Checking
We apply the symbolic analysis principle to pushdown systems. We represent (possibly in nite) sets of con gurations of such systems by means of nite-state automata. In order to re...
Ahmed Bouajjani, Javier Esparza, Oded Maler
120
Voted
CHARME
2003
Springer
97views Hardware» more  CHARME 2003»
15 years 9 months ago
Convergence Testing in Term-Level Bounded Model Checking
We consider the problem of bounded model checking of systems expressed in a decidable fragment of first-order logic. While model checking is not guaranteed to terminate for an ar...
Randal E. Bryant, Shuvendu K. Lahiri, Sanjit A. Se...