135 search results - page 23 / 27 » Model Checking Timed Automata with One or Two Clocks |
144
click to vote
EMSOFT
2006
Springer
15 years 7 months ago
2006
Springer
We report on a case study in which the model checker Uppaal is used to formally model parts of Zeroconf, a protocol for dynamic configuration of IPv4 link-local addresses that has...
128
click to vote
DATE
2004
IEEE
2004
IEEE
Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements
15 years 8 months ago
We show how to automatically verify that complex XScale-like pipelined machine models satisfy the same safety and liveness properties as their corresponding instruction set archit...
117
click to vote
ACISICIS
2010
IEEE
15 years 5 months ago
2010
IEEE
Recently, software size becomes larger, and consequently, not only a software developer but also a software purchaser suffers considerable losses by software project failure. So av...
140
click to vote
ISCAS
2008
IEEE
15 years 10 months ago
2008
IEEE
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
118
click to vote
TCAD
2010
14 years 11 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...