22 search results - page 1 / 5 » Model Checking Verilog Descriptions of Cell Libraries |
68
Voted
ACSD
2009
IEEE
15 years 5 months ago
2009
IEEE
We present a formal semantics for a subset of Verilog, commonly used to describe cell libraries, in terms of transition systems. Such transition systems can serve as input to symb...
DATE
2010
IEEE
15 years 3 months ago
2010
IEEE
—Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Sp...
FMICS
2009
Springer
15 years 4 months ago
2009
Springer
Cell libraries often contain a simulation model in a system design language, such as Verilog. These languages usually involve nondeterminism, which in turn, poses a challenge to th...
FMCAD
2000
Springer
15 years 1 months ago
2000
Springer
Abstract. Since the advent of model checking it is becoming more common for languages to be given a semantics in terms of transition systems. Such semantics allow to model check pr...
ICCAD
2004
IEEE
15 years 7 months ago
2004
IEEE
edicate Abstraction and Induction Edmund Clarke Daniel Kroening June 25, 2004 CMU-CS-04-131 School of Computer Science Carnegie Mellon University Pittsburgh, PA 15213 It is common...