Abstract. Default logic is one of the most widely used formalisms to formalize commonsense reasoning. In this paper we analyze the complexity of deciding whether a propositional in...
This paper presents a case study for automatic verification using the Communicating Sequential Processes formalism. The case study concerns the Futurebus+ cache coherency standard...
Timed Concurrent State Machines are an application of Alur’s Timed Automata concept to coincidence-based (rather than interleaving) CSM modeling technique. TCSM support the idea...
This paper provides an experimental study of the efficiency of simulation-based model-checking algorithms for continuous-time Markov chains by comparing: MRMC – the only tool t...
toolkit demonstrates that predicate abstraction enables automated verification of real world Windows device Our predicate abstraction-based tool DDVerify enables the automated ve...
Thomas Witkowski, Nicolas Blanc, Daniel Kroening, ...