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» Model Checking and Transitive-Closure Logic
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93
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BELL
2000
107views more  BELL 2000»
14 years 10 months ago
Automating software feature verification
A significant part of the call processing software for Lucent's new PathStar access server [FSW98] was checked with automated formal verification techniques. The verification...
Gerard J. Holzmann, Margaret H. Smith
85
Voted
DAC
2006
ACM
15 years 12 months ago
Transistor abstraction for the functional verification of FPGAs
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
Guy Dupenloup, Thierry Lemeunier, Roland Mayr
101
Voted
ATVA
2006
Springer
133views Hardware» more  ATVA 2006»
15 years 2 months ago
Branching-Time Property Preservation Between Real-Time Systems
In the past decades, many formal frameworks (e.g. timed automata and temporal logics) and techniques (e.g. model checking and theorem proving) have been proposed to model a real-ti...
Jinfeng Huang, Marc Geilen, Jeroen Voeten, Henk Co...
FOAL
2008
ACM
15 years 13 days ago
Incremental analysis of interference among aspects
Often, insertion of several aspects into one system is desired and in that case the problem of interference among the different aspects might arise, even if each aspect individual...
Emilia Katz, Shmuel Katz
108
Voted
FDL
2004
IEEE
15 years 2 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng