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» Model Checking for Programming Languages using Verisoft
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KBSE
2005
IEEE
15 years 10 months ago
Automated test generation for engineering applications
In test generation based on model-checking, white-box test criteria are represented as trap conditions written in a temporal logic. A model checker is used to refute trap conditio...
Songtao Xia, Ben Di Vito, César Muño...

Book
260views
17 years 24 days ago
Java Look and Feel Design Guidelines
"Although an application's human interface designer and software developer might well be the same person, the two jobs involve different tasks and require different skill...
Sun Microsystems Inc
IFIP
2009
Springer
15 years 11 months ago
Static Detection of Logic Flaws in Service-Oriented Applications
Application or business logic, used in the development of services, has to do with the operations that define the application functionalities and not with the platform ones. Often...
Chiara Bodei, Linda Brodo, Roberto Bruni
CADE
2008
Springer
16 years 5 months ago
Automated Induction with Constrained Tree Automata
We propose a procedure for automated implicit inductive theorem proving for equational specifications made of rewrite rules with conditions and constraints. The constraints are int...
Adel Bouhoula, Florent Jacquemard
ASYNC
2007
IEEE
129views Hardware» more  ASYNC 2007»
15 years 9 months ago
Formal Verification of CHP Specifications with CADP Illustration on an Asynchronous Network-on-Chip
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
Gwen Salaün, Wendelin Serwe, Yvain Thonnart, ...