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CODES
2009
IEEE
16 years 5 days ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
ICCS
2004
Springer
15 years 10 months ago
Using Runtime Measurements and Historical Traces for Acquiring Knowledge in Parallel Applications
Abstract. A new approach for acquiring knowledge of parallel applications regarding resource usage and for searching similarity on workload traces is presented. The main goal is to...
Luciano José Senger, Marcos José San...
IPPS
2000
IEEE
15 years 9 months ago
Controlling Distributed Shared Memory Consistency from High Level Programming Languages
One of the keys for the success of parallel processing is the availability of high-level programming languages for on-the-shelf parallel architectures. Using explicit message passi...
Yvon Jégou
FCCM
2009
IEEE
147views VLSI» more  FCCM 2009»
15 years 9 months ago
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks
Artificial neural networks are a key tool for researchers attempting to understand and replicate the behaviour and intelligence found in biological neural networks. Software simul...
David Thomas, Wayne Luk
GI
2005
Springer
15 years 11 months ago
Analysis and Design Techniques for Service-Oriented Development and Integration
: Service-Oriented Architectures (SOAs) have been established as an IT strategy to support the on demand goal of business agility. Web services standards and their implementations ...
Olaf Zimmermann, Niklas Schlimm, Günter Walle...