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AMAST
2010
Springer
14 years 4 months ago
Integrating Maude into Hets
Maude modules can be understood as models that can be formally analyzed and verified with respect to different properties expressing various formal requirements. However, Maude lac...
Mihai Codescu, Till Mossakowski, Adrián Rie...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
15 years 10 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
FOSSACS
2010
Springer
15 years 4 months ago
On the Relationship between Spatial Logics and Behavioral Simulations
Abstract. Spatial logics have been introduced to reason about distributed computation in models for concurrency. We first define a spatial logic for a general class of infinite-...
Lucia Acciai, Michele Boreale, Gianluigi Zavattaro
ICIW
2007
IEEE
15 years 1 months ago
Type-Based Static and Dynamic Website Verification
Abstract-- Maintaining large websites and verifying their semantic content is a difficult task. In this paper we propose a framework for syntactic validation, semantic verification...
Jorge Coelho, Mário Florido
QEST
2007
IEEE
15 years 4 months ago
Performance Trees: Expressiveness and Quantitative Semantics
—Performance Trees are a recently-proposed mechanism for the specification of performance properties and measures. They represent an attractive alternative to stochastic logics,...
Tamas Suto, Jeremy T. Bradley, William J. Knottenb...