Maude modules can be understood as models that can be formally analyzed and verified with respect to different properties expressing various formal requirements. However, Maude lac...
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Abstract. Spatial logics have been introduced to reason about distributed computation in models for concurrency. We first define a spatial logic for a general class of infinite-...
Abstract-- Maintaining large websites and verifying their semantic content is a difficult task. In this paper we propose a framework for syntactic validation, semantic verification...
—Performance Trees are a recently-proposed mechanism for the specification of performance properties and measures. They represent an attractive alternative to stochastic logics,...
Tamas Suto, Jeremy T. Bradley, William J. Knottenb...