756 search results - page 109 / 152 » Model Order Reduction for Nonlinear IC Models |
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
SEFM
2009
IEEE
15 years 4 months ago
2009
IEEE
Interval temporal logics are based on interval structures over linearly (or partially) ordered domains, where time intervals, rather than time instants, are the primitive ontologi...
ICCAD
1996
IEEE
15 years 1 months ago
1996
IEEE
While numerous power optimization techniques have been at all levels of design process abstractions for electronic components, until now, power minimization in mixed mechanical-el...
TCAD
2010
14 years 4 months ago
2010
Abstract--An efficient passivity test based on canonical projector techniques is proposed for descriptor systems (DSs) widely encountered in circuit and system modeling. The test f...