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» Model Order Reduction for Nonlinear IC Models
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KBSE
2007
IEEE
15 years 4 months ago
Test suite reduction and prioritization with call trees
This paper presents a tool that (i) constructs tree-based models of a program’s behavior during testing and (ii) employs these trees while reordering and reducing a test suite. ...
Adam M. Smith, Joshua Geiger, Gregory M. Kapfhamme...
PATMOS
2004
Springer
15 years 3 months ago
Sleepy Stack Reduction of Leakage Power
Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as...
Jun-Cheol Park, Vincent John Mooney III, Philipp P...
DEON
2006
Springer
15 years 1 months ago
Strategic Deontic Temporal Logic as a Reduction to ATL, with an Application to Chisholm's Scenario
In this paper we extend earlier work on deontic deadlines in CTL to the framework of alternating time temporal logic (ATL). The resulting setting enables us to model several concep...
Jan Broersen
AISS
2010
147views more  AISS 2010»
14 years 7 months ago
Correlating Lattice Constant of Cubic Perovskites to Atomic Parameters Using Support Vector Regression
Recently, due to problems arising from lattice mismatch in thin film growth in semiconductor manufacturing industry, researchers have shown great interest in modeling the physioch...
Abdul Majid, Yeon Soo Lee
ICMCS
2005
IEEE
158views Multimedia» more  ICMCS 2005»
15 years 3 months ago
Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicat...
Min Li, Xiaobo Wu, Zihua Guo, Richard Yao, Xiaolan...