Sciweavers

733 search results - page 113 / 147
» Model Reuse through Hardware Design Patterns
Sort
View
ASPDAC
2008
ACM
200views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Non-Gaussian statistical timing analysis using second-order polynomial fitting
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
Lerong Cheng, Jinjun Xiong, Lei He
85
Voted
DAC
2011
ACM
13 years 9 months ago
AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection
In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design i...
Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan
MMM
2005
Springer
172views Multimedia» more  MMM 2005»
15 years 3 months ago
A Novel Approach of 3D Reconstruction of Human Face Using Monocular Camera
Three-dimensional model acquisition of an object is essential in many multimedia applications. Constructing three-dimensional models of objects from two-dimensional images is an o...
Ben Yip, Jesse S. Jin
EUROMICRO
2007
IEEE
15 years 4 months ago
Partial Verification of Software Components: Heuristics for Environment Construction
Code model checking of software components suffers from the well-known problem of state explosion when applied to highly parallel components, despite the fact that a single compon...
Pavel Parizek, Frantisek Plasil
ISCAS
2005
IEEE
127views Hardware» more  ISCAS 2005»
15 years 3 months ago
Energy and latency evaluation of NoC topologies
Abstract — Mapping applications onto different networks-onchip (NoCs) topologies is done by mapping processing cores on local ports of routers considering requirements like laten...
Márcio Eduardo Kreutz, César A. M. M...