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» Model Reuse through Hardware Design Patterns
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ECBS
2005
IEEE
126views Hardware» more  ECBS 2005»
15 years 3 months ago
Toward Introducing Notification Technology into Distributed Project Teams
Software development can be thought of as the evolution act requirements into a concrete software system. The evolution, achieved through a successive series of elaborations and r...
Jamie L. Smith, Shawn A. Bohner, D. Scott McCricka...
EUROPAR
2003
Springer
15 years 2 months ago
Obtaining Hardware Performance Metrics for the BlueGene/L Supercomputer
Hardware performance monitoring is the basis of modern performance analysis tools for application optimization. We are interested in providing such performance analysis tools for t...
Pedro Mindlin, José R. Brunheroto, Luiz De ...
ISQED
2005
IEEE
140views Hardware» more  ISQED 2005»
15 years 3 months ago
Toward Quality EDA Tools and Tool Flows Through High-Performance Computing
As the scale and complexity of VLSI circuits increase, Electronic Design Automation (EDA) tools become much more sophisticated and are held to increasing standards of quality. New...
Aaron N. Ng, Igor L. Markov
78
Voted
ISCA
2008
IEEE
150views Hardware» more  ISCA 2008»
15 years 4 months ago
Fetch-Criticality Reduction through Control Independence
Architectures that exploit control independence (CI) promise to remove in-order fetch bottlenecks, like branch mispredicts, instruction-cache misses and fetch unit stalls, from th...
Mayank Agarwal, Nitin Navale, Kshitiz Malik, Matth...
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
15 years 4 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...