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» Model Reuse through Hardware Design Patterns
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VTS
2005
IEEE
116views Hardware» more  VTS 2005»
15 years 3 months ago
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
Kartik Mohanram
IWCMC
2006
ACM
15 years 3 months ago
Radio propagation patterns in wireless sensor networks: new experimental results
Wireless sensors use low power radio transceivers due to the stringent constraints on battery capacity. As a result, radio transmission with wireless sensors is unreliable. Furthe...
Tereus Scott, Kui Wu, Daniel Hoffman
ICECCS
2008
IEEE
140views Hardware» more  ICECCS 2008»
15 years 4 months ago
A Formal Model of Semantic Web Service Ontology (WSMO) Execution
Semantic Web Services have been one of the most significant research areas within the Semantic Web vision, and have been recognized as a promising technology that exhibits huge c...
Hai H. Wang, Nick Gibbins, Terry R. Payne, Ahmed S...
DAC
2006
ACM
15 years 1 months ago
Refined statistical static timing analysis through
Statistical static timing analysis (SSTA) has been a popular research topic in recent years. A fundamental issue with applying SSTA in practice today is the lack of reliable and e...
Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Cycle error correction in asynchronous clock modeling for cycle-based simulation
— As the complexity of SoCs is increasing, hardware/software co-verification becomes an important part of system verification. C-level cycle-based simulation could be an efficien...
Junghee Lee, Joonhwan Yi