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» Model Reuse through Hardware Design Patterns
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MICRO
2010
IEEE
130views Hardware» more  MICRO 2010»
14 years 7 months ago
Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for ...
Minseon Ahn, Eun Jung Kim
ASPDAC
2009
ACM
212views Hardware» more  ASPDAC 2009»
15 years 4 months ago
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
Abstract— Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes...
Kwangok Jeong, Andrew B. Kahng
SERP
2008
14 years 11 months ago
Object-Oriented Hypermedia Design and J2EE Technology for Web-based Applications
Web-based application development is a difficult task, since these applications include various features, like graphical interfaces, navigational structures, business models, and ...
Habib Karimpour, Ayaz Isazadeh, Mohsen Heydarian
DATE
2007
IEEE
112views Hardware» more  DATE 2007»
15 years 4 months ago
Tool-support for the analysis of hybrid systems and models
This paper introduces a method and tool-support for the automatic analysis and verification of hybrid and embedded control systems, whose continuous dynamics are often modelled u...
Andreas Bauer 0002, Markus Pister, Michael Tautsch...
ANCS
2011
ACM
13 years 9 months ago
ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization
Network virtualization has emerged as a powerful technique to deploy novel services and experimental protocols over shared network infrastructures. Although recent research has hi...
Deepak Unnikrishnan, Justin Lu, Lixin Gao, Russell...