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» Model Reuse through Hardware Design Patterns
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2009
ACM
15 years 2 months ago
A framework for core-level modeling and design of reconfigurable computing algorithms
Reconfigurable computing (RC) is rapidly becoming a vital technology for many applications, from high-performance computing to embedded systems. The inherent advantages of custom-...
Gongyu Wang, Greg Stitt, Herman Lam, Alan D. Georg...
ISCA
2010
IEEE
240views Hardware» more  ISCA 2010»
15 years 2 months ago
Modeling critical sections in Amdahl's law and its implications for multicore design
This paper presents a fundamental law for parallel performance: it shows that parallel performance is not only limited by sequential code (as suggested by Amdahl’s law) but is a...
Stijn Eyerman, Lieven Eeckhout
ISQED
2003
IEEE
119views Hardware» more  ISQED 2003»
15 years 3 months ago
System and Framework for QA of Process Design Kits
In this paper, we evaluate the dependencies between tools, data and environment in process design kits, and present a framework for systematically analyzing the quality of the des...
M. C. Scott, M. O. Peralta, Jo Dale Carothers
FCCM
2005
IEEE
107views VLSI» more  FCCM 2005»
15 years 3 months ago
Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller
As technology sizes decrease and die area increases, designers are creating increasingly complex computing systems using FPGAs. To reduce design time for new products, the reuse o...
Lesley Shannon, Paul Chow
ISQED
2003
IEEE
303views Hardware» more  ISQED 2003»
15 years 3 months ago
Design and Analysis of Low-Voltage Current-Mode Logic Buffers
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
Payam Heydari