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» Model Reuse through Hardware Design Patterns
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DATE
2002
IEEE
99views Hardware» more  DATE 2002»
15 years 2 months ago
Gate Level Fault Diagnosis in Scan-Based BIST
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
Ismet Bayraktaroglu, Alex Orailoglu
MSWIM
2006
ACM
15 years 3 months ago
Pattern matching based link quality prediction in wireless mobile ad hoc networks
As mobile devices, such as laptops, PDAs or mobile phones, are getting more and more ubiquitous and are able to communicate with each other via wireless technologies, the paradigm...
Károly Farkas, Theus Hossmann, Lukas Ruf, B...
GECCO
2006
Springer
137views Optimization» more  GECCO 2006»
15 years 1 months ago
Evolutionary design of fault-tolerant analog control for a piezoelectric pipe-crawling robot
In this paper, a genetic algorithm (GA) is used to design faulttolerant analog controllers for a piezoelectric micro-robot. Firstorder and second-order functions are developed to ...
Geoffrey A. Hollinger, David A. Gwaltney
ISARCS
2010
141views Hardware» more  ISARCS 2010»
15 years 1 months ago
Integrating Fault-Tolerant Techniques into the Design of Critical Systems
Abstract. Software designs equipped with specification of dependability techniques can help engineers to develop critical systems. In this work, we start to envision how a softwar...
Ricardo J. Rodríguez, José Merseguer
ASPDAC
2008
ACM
103views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Reliability-aware design for nanometer-scale devices
Continuous transistor scaling due to improvements in CMOS devices and manufacturing technologies is increasing processor power densities and temperatures; thus, creating challenges...
David Atienza, Giovanni De Micheli, Luca Benini, J...