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» Model Reuse through Hardware Design Patterns
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LCPC
2004
Springer
15 years 3 months ago
Phase-Based Miss Rate Prediction Across Program Inputs
Previous work shows the possibility of predicting the cache miss rate (CMR) for all inputs of a program. However, most optimization techniques need to know more than the miss rate ...
Xipeng Shen, Yutao Zhong, Chen Ding
MSWIM
2009
ACM
15 years 4 months ago
Designing an asynchronous group communication middleware for wireless users
We evaluate an asynchronous gossiping middleware for wireless users that propagates messages from any group member to all the other group members. This propagation can either be i...
Xuwen Yu, Surendar Chandra
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
15 years 3 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
SIGPLAN
2008
14 years 9 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
TCAD
2002
146views more  TCAD 2002»
14 years 9 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier