733 search results - page 84 / 147 » Model Reuse through Hardware Design Patterns |
ICECCS
2009
IEEE
15 years 4 months ago
2009
IEEE
Distributed information systems are critical to the functioning of many businesses; designing them to be dependable is a challenging but important task. We report our experience i...
CAV
2006
Springer
15 years 1 months ago
2006
Springer
Example Guided Abstraction Refinement (CEGAR) [6] framework. A number of wellengineered software model-checkers are available, e.g., SLAM [1] and BLAST [12]. Why build another one?...
107
click to vote
IWOMP
2007
Springer
15 years 3 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
In mixed-signal designs, substrate noise originating from the digital part can seriously influence the functionality of the analog part. As such, accurately modeling the properti...