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» Model checking SystemC designs using timed automata
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FM
2009
Springer
163views Formal Methods» more  FM 2009»
15 years 2 months ago
Analysis of a Clock Synchronization Protocol for Wireless Sensor Networks
We study a clock synchronization protocol for the Chess WSN. First, we model the protocol as a network of timed automata and verify various instances using the Uppaal model checker...
Faranak Heidarian, Julien Schmaltz, Frits W. Vaand...
FDL
2003
IEEE
15 years 2 months ago
Using Symbolic Simulation for Bounded Property Checking
Assuring correctness of digital designs is one of the major tasks in the system design flow. Formal methods have been proposed to accompany commonly used simulation approaches. I...
Jürgen Ruf, Prakash Mohan Peranandam, Thomas ...
FATES
2004
Springer
15 years 2 months ago
Testing Deadlock-Freeness in Real-Time Systems: A Formal Approach
A Time Action Lock is a state of a Real-time system at which neither time can progress nor an action can occur. Time Action Locks are often seen as signs of errors in the model or ...
Behzad Bordbar, Kozo Okano
EPK
2006
114views Management» more  EPK 2006»
14 years 10 months ago
Verifying Properties of (Timed) Event Driven Process Chains by Transformation to Hybrid Automata
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...
Stefan Denne
JTRES
2010
ACM
14 years 9 months ago
The design of SafeJML, a specification language for SCJ with support for WCET specification
Safety-Critical Java (SCJ) is a dialect of Java that allows programmers to implement safety-critical systems, such as software to control airplanes, medical devices, and nuclear p...
Ghaith Haddad, Faraz Hussain, Gary T. Leavens