288 search results - page 43 / 58 » Model checking SystemC designs using timed automata |
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FDL
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
DAC
2004
ACM
15 years 10 months ago
2004
ACM
ion of Assembler Programs for Symbolic Worst Case Execution Time Analysis Tobias Schuele Tobias.Schuele@informatik.uni-kl.de Klaus Schneider Klaus.Schneider@informatik.uni-kl.de Re...
FSTTCS
2009
Springer
15 years 4 months ago
2009
Springer
The paper focuses on the structure of fundamental sequences of ordinals smaller than ε0. A first result is the construction of a monadic second-order formula identifying a given ...
SIMUTOOLS
2008
14 years 10 months ago
2008
We sketch the fundamental properties and features of Snoopy, a tool to model and execute (animate, simulate) hierarchical graph-based system descriptions. The tool comes along wit...
TCAD
2010
14 years 4 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...