364 search results - page 41 / 73 » Model checking with Boolean Satisfiability |
107
Voted
DAC
2003
ACM
16 years 3 months ago
2003
ACM
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
109
Voted
ICNP
2007
IEEE
15 years 9 months ago
2007
IEEE
- A Network Court Protocol is designed for malicious node conviction based on information from network node accusing and testifying operations, which are formally modeled by algebr...
165
Voted
DLT
2009
15 years 12 days ago
2009
Abstract. Temporal logics are a well investigated formalism for the specification and verification of reactive systems. Using formal verification techniques, we can ensure the corr...
123
Voted
ICFEM
2004
Springer
15 years 8 months ago
2004
Springer
d Abstract) Carsten Sinz and Wolfgang K¨uchlin Symbolic Computation Group, WSI for Computer Science, University of T¨ubingen and Steinbeis Technology Transfer Center OIT, 72076 T...
113
Voted
SIGSOFT
2005
ACM
16 years 3 months ago
2005
ACM
We present a technique that enables the use of finite model finding to check the satisfiability of certain formulas whose intended models are infinite. Such formulas arise when us...