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GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
15 years 10 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
ISORC
1998
IEEE
15 years 10 months ago
The Time-Triggered Architecture
The Time-Triggered Architecture (TTA) provides a computing infrastructure for the design and implementation of dependable distributed embedded systems. A large real-time applicatio...
Hermann Kopetz
ISSS
1998
IEEE
124views Hardware» more  ISSS 1998»
15 years 10 months ago
Data-Path Synthesis of VLIW Video Signal Processors
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
Zhao Wu, Wayne Wolf
VRML
1998
ACM
15 years 10 months ago
3D Product Presentation Online: The Virtual Design Exhibition
VRML offers a high potential for product presentation: Instead of regarding flat, static pictures, configurable and animated 3D models embedded in entertaining environments provid...
J. Dauner, Jürgen Landauer, E. Stimpfig, D. R...
IFIP
1998
Springer
15 years 10 months ago
Combining Static Partitioning with Dynamic Distribution of Threads
This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel an...
Ronald Moore, Melanie Klang, Bernd Klauer, Klaus W...