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» Model-Order Reduction Based on PRONY's Method
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ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
15 years 1 months ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
117
Voted
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
15 years 9 months ago
Random sampling of moment graph: a stochastic Krylov-reduction algorithm
In this paper we introduce a new algorithm for model order reduction in the presence of parameter or process variation. Our analysis is performed using a graph interpretation of t...
Zhenhai Zhu, Joel R. Phillips
115
Voted
DATE
2007
IEEE
126views Hardware» more  DATE 2007»
15 years 9 months ago
WAVSTAN: waveform based variational static timing analysis
— We present a waveform based variational static timing analysis methodology. It is a timing paradigm that lies midway between convention static delay approximations and full dyn...
Saurabh K. Tiwary, Joel R. Phillips
DATE
2008
IEEE
170views Hardware» more  DATE 2008»
15 years 10 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
ASPDAC
2008
ACM
130views Hardware» more  ASPDAC 2008»
15 years 5 months ago
Architecture-level thermal behavioral characterization for multi-core microprocessors
In this paper, we investigate a new architecture-level thermal characterization problem from behavioral modeling perspective to address the emerging thermal related analysis and o...
Duo Li, Sheldon X.-D. Tan, Murli Tirumala