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ICFEM
2004
Springer
15 years 6 months ago
Linear Inequality LTL (iLTL): A Model Checker for Discrete Time Markov Chains
Abstract. We develop a way of analyzing the behavior of systems modeled using Discrete Time Markov Chains (DTMC). Specifically, we define iLTL, an LTL with linear inequalities on...
YoungMin Kwon, Gul Agha
103
Voted
FMCAD
2009
Springer
15 years 4 months ago
Industrial strength refinement checking
This paper discusses a methodology used on an industrial hardware development project to validate various cache-coherence protocol components. The idea is to use a high level model...
Jesse D. Bingham, John Erickson, Gaurav Singh, Fle...
DATE
2010
IEEE
126views Hardware» more  DATE 2010»
15 years 4 months ago
Scenario-based analysis and synthesis of real-time systems using uppaal
Abstract. We propose an approach to scenario-based analysis and synthesis of real-time embedded systems. The inter-process behaviors of a system are modeled as a set of driving uni...
Kim Guldstrand Larsen, Shuhao Li, Brian Nielsen, S...
112
Voted
ECAI
2008
Springer
15 years 2 months ago
Learning in Planning with Temporally Extended Goals and Uncontrollable Events
Recent contributions to advancing planning from the classical model to more realistic problems include using temporal logic such as LTL to express desired properties of a solution ...
André A. Ciré, Adi Botea
ENTCS
2006
142views more  ENTCS 2006»
15 years 22 days ago
Predicate Diagrams for the Verification of Real-Time Systems
We propose a format of predicate diagrams for the verification of real-time systems. We consider systems that are defined as extended timed graphs, a format that combines timed au...
Eun-Young Kang, Stephan Merz