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DATE
2006
IEEE
127views Hardware» more  DATE 2006»
15 years 9 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
152
Voted
LCTRTS
2010
Springer
15 years 10 months ago
Elastic computing: a framework for transparent, portable, and adaptive multi-core heterogeneous computing
Over the past decade, system architectures have started on a clear trend towards increased parallelism and heterogeneity, often resulting in speedups of 10x to 100x. Despite numer...
John Robert Wernsing, Greg Stitt
119
Voted
IEEEPACT
2008
IEEE
15 years 9 months ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...
170
Voted
JEI
2006
162views more  JEI 2006»
15 years 3 months ago
Markovian segmentation and parameter estimation on graphics hardware
In this paper, we show how Markovian strategies used to solve well-known segmentation problems such as motion estimation, motion detection, motion segmentation, stereovision, and c...
Pierre-Marc Jodoin, Max Mignotte
IPPS
2009
IEEE
15 years 10 months ago
High-level estimation and trade-off analysis for adaptive real-time systems
We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accu...
Ingo Sander, Jun Zhu, Axel Jantsch, Andreas Herrho...