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» Model-integrated parallel application synthesis
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DAC
2008
ACM
15 years 10 months ago
Daedalus: toward composable multimedia MP-SoC design
Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which ...
Hristo Nikolov, Mark Thompson, Todor Stefanov, And...
FPGA
2006
ACM
224views FPGA» more  FPGA 2006»
15 years 1 months ago
Flexible implementation of genetic algorithms on FPGAs
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shiba...
ASAP
2005
IEEE
142views Hardware» more  ASAP 2005»
15 years 3 months ago
Decimal Floating-Point Square Root Using Newton-Raphson Iteration
With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth...
Liang-Kai Wang, Michael J. Schulte
EMSOFT
2004
Springer
15 years 2 months ago
Loose synchronization of event-triggered networks for distribution of synchronous programs
Dataflow synchronous languages have attracted considerable interest in domains such as real-time control and hardware design. The potential benefits are promising: Discrete-time...
Jan Romberg, Andreas Bauer 0002
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
15 years 6 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...