168 search results - page 10 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
MEMOCODE
2003
IEEE
15 years 2 months ago
2003
IEEE
In this paper, we present a technique for determining tight bounds on the execution time of assembler programs. Thus, our method is independent of the design flow, but takes into...
LCPC
2004
Springer
15 years 2 months ago
2004
Springer
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
IEEEPACT
2003
IEEE
15 years 2 months ago
2003
IEEE
Effective modeling and management of hardware resources have always been critical toward generating highly efficient code in static compilers. With Just-In-Time compilation and dy...
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CASES
2007
ACM
15 years 1 months ago
2007
ACM
With increasing complexity of modern embedded systems, the availability of highly optimizing compilers becomes more and more important. At the same time, application specific inst...
CJ
2006
14 years 9 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...