168 search results - page 11 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
144
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DAC
2003
ACM
15 years 2 months ago
2003
ACM
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...
105
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DSRT
2008
IEEE
14 years 11 months ago
2008
IEEE
Most common real-time embedded programming languages provide a means to specify functionality; however, they have few constructs to specify precise timing constraints. LabVIEW is ...
108
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ASPLOS
2000
ACM
15 years 1 months ago
2000
ACM
This paper presents the first analysis of operating system execution on a simultaneous multithreaded (SMT) processor. While SMT has been studied extensively over the past 6 years,...
ICCAD
1994
IEEE
15 years 1 months ago
1994
IEEE
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
116
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ISCAPDCS
2004
14 years 10 months ago
2004
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...