168 search results - page 12 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
ICRA
1995
IEEE
15 years 1 months ago
1995
IEEE
A generic architecture for evolutive supervision of robotized assembly tasks is presented. This architecture , at different levels of abstraction, functions for dispatching action...
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DAC
1995
ACM
15 years 1 months ago
1995
ACM
Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade–off between flexibility and cost. However, existing code generation metho...
DAC
1999
ACM
15 years 10 months ago
1999
ACM
Abstract { This paper presents the machine description language LISA for the generation of bitand cycle accurate models of DSP processors. Based on a behavioral operation descripti...
HICSS
1995
IEEE
15 years 1 months ago
1995
IEEE
Abstract. We reexamine the limits of parallelism available in programs, using runtime reconstruction of program data-flow graphs. While limits of parallelism have been examined in...
WCET
2008
14 years 11 months ago
2008
WCET analysis models for superscalar out-of-order CPUs generally need to be pessimistic in order to account for a wide range of possible dynamic behavior. CPU hardware modificatio...