168 search results - page 13 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
DAC
2012
ACM
12 years 12 months ago
2012
ACM
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
113
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HPCA
2005
IEEE
15 years 9 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
90
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JUCS
2000
14 years 9 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
68
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ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
RSP
2000
IEEE
15 years 1 months ago
2000
IEEE
This paper describes a methodology for developing processor specific tools such as assemblers, disassemblers, processor simulators, compilers etc., using processor models in a ge...