168 search results - page 14 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
ISCA
2005
IEEE
15 years 3 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
TCAD
2002
14 years 9 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
ASPDAC
2005
ACM
14 years 11 months ago
2005
ACM
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
ISCA
1999
IEEE
15 years 1 months ago
1999
IEEE
Modern compilers must expose sufficient amounts of Instruction-Level Parallelism (ILP) to achieve the promised performance increases of superscalar and VLIW processors. One of the...
ISCA
2000
IEEE
15 years 1 months ago
2000
IEEE
The register file access time is one of the critical delays in current superscalar processors. Its impact on processor performance is likely to increase in future processor genera...