168 search results - page 16 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
CADE
2007
Springer
15 years 9 months ago
2007
Springer
Abstract. The verification of device drivers is essential for the pervasive verification of an operating system. To show the correctness of device drivers, devices have to be forma...
ERSA
2003
14 years 10 months ago
2003
Abstract— Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the har...
HICSS
1995
IEEE
15 years 1 months ago
1995
IEEE
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
SIGMETRICS
1995
ACM
15 years 1 months ago
1995
ACM
Talisman is a simulator that models the execution semantics and timing of a multicomputer. Talisman is unique in combining high semantic accuracy, high timing accuracy, portabilit...
WSC
1997
14 years 10 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...