168 search results - page 20 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
SIGGRAPH
2010
ACM
15 years 1 months ago
2010
ACM
We introduce an interactive tool which enables a user to quickly assemble an architectural model directly over a 3D point cloud acquired from large-scale scanning of an urban scen...
ISCA
2006
IEEE
14 years 9 months ago
2006
IEEE
: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...
IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...
VLSID
2007
IEEE
15 years 9 months ago
2007
IEEE
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
ICCD
2005
IEEE
15 years 3 months ago
2005
IEEE
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...