168 search results - page 24 / 34 » Modeling Assembly Instruction Timing in Superscalar Architec... |
PDPTA
2004
14 years 10 months ago
2004
We present the MBRAM model for static evaluation of the performance of memory-bound programs. The MBRAM model predicts the actual running time of a memory-bound program directly fr...
115
Voted
ECRTS
2007
IEEE
15 years 3 months ago
2007
IEEE
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
CGF
2006
14 years 9 months ago
2006
WPSD (Weighted Pose Space Deformation) is an example based skinning method for articulated body animation. The per-vertex computation required in WPSD can be parallelized in a SIM...
CGO
2005
IEEE
15 years 3 months ago
2005
IEEE
Register allocation is one of the most important optimizations a compiler performs. Conventional graphcoloring based register allocators are fast and do well on regular, RISC-like...
FPL
2004
Springer
15 years 2 months ago
2004
Springer
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...