356 search results - page 23 / 72 » Modeling Cache Sharing on Chip Multiprocessor Architectures |
162
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ASPLOS
1998
ACM
15 years 9 months ago
1998
ACM
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
155
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RTAS
2010
IEEE
15 years 3 months ago
2010
IEEE
Abstract--Modern computing systems have adopted multicore architectures and multiprocessor systems on chip (MPSoCs) for accommodating the increasing demand on computation power. Ho...
149
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IEEEPACT
2006
IEEE
15 years 11 months ago
2006
IEEE
The role of the operating system (OS) in managing shared resources such as CPU time, memory, peripherals, and even energy is well motivated and understood [23]. Unfortunately, one...
128
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DATE
2004
IEEE
15 years 9 months ago
2004
IEEE
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
153
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IPPS
2006
IEEE
15 years 11 months ago
2006
IEEE
Chip multiprocessors (CMPs) are becoming a popular way of exploiting ever-increasing number of on-chip transistors. At the same time, the location of data on the chip can play a c...