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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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HPCA
2006
IEEE
16 years 5 months ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...
160
Voted
DAC
2004
ACM
15 years 10 months ago
Extending the transaction level modeling approach for fast communication architecture exploration
System-on-Chip (SoC) designs are increasingly becoming more complex. Efficient on-chip communication architectures are critical for achieving desired performance in these systems....
Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdha...
NOCS
2009
IEEE
16 years 2 days ago
Best of both worlds: A bus enhanced NoC (BENoC)
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficie...
Ran Manevich, Isask'har Walter, Israel Cidon, Avin...
155
Voted
POS
1998
Springer
15 years 9 months ago
DynamO: Dynamic Objects with Persistent Storage
In light of advances in processor and networking technology, especially the emergence of network attached disks, the traditional client-server architecture becomes suboptimal for ...
Jiong Yang, Silvia Nittel, Wei Wang 0010, Richard ...
VLDB
2005
ACM
121views Database» more  VLDB 2005»
15 years 10 months ago
Improving Database Performance on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. Because threads share processor resources,...
Jingren Zhou, John Cieslewicz, Kenneth A. Ross, Mi...