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» Modeling Cache Sharing on Chip Multiprocessor Architectures
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MICRO
2009
IEEE
115views Hardware» more  MICRO 2009»
15 years 6 months ago
SHARP control: controlled shared cache management in chip multiprocessors
Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang
ASPLOS
2008
ACM
15 years 1 months ago
Adaptive set pinning: managing shared caches in chip multiprocessors
Shekhar Srikantaiah, Mahmut T. Kandemir, Mary Jane...
ISHPC
1999
Springer
15 years 3 months ago
Utilization of Cache Area in On-Chip Multiprocessor
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
Hitoshi Oi, N. Ranganathan
CAL
2010
14 years 9 months ago
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 4 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...